HD6413007F20 Datasheet, PDF (496/798 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

13. Serial Communication Interface
Figure 13.8 shows an example of SCI receive operation in asynchronous mode.
1
RDRF
FER
Start
bit
Data
Parity Stop Start
bit bit bit
Stop Parity Stop
Data _{bit bit bit}
1
0 D0 D1
D7 0/1 1 0 D0 D1
D7 0/1 1
Idle (mark) state
1 frame
RXI request
RXI interrupt handler
reads data in RDR and
clears RDRF flag to 0
Framing error,
ERI request
Figure 13.8 Example of SCI Receive Operation (8-Bit Data with Parity and One Stop Bit)
13.3.3 Multiprocessor Communication
The multiprocessor communication function enables several processors to share a single serial
communication line. The processors communicate in asynchronous mode using a format with an
additional multiprocessor bit (multiprocessor format).
In multiprocessor communication, each receiving processor is addressed by an ID. A serial
communication cycle consists of an ID-sending cycle that identifies the receiving processor, and a
data-sending cycle. The multiprocessor bit distinguishes ID-sending cycles from data-sending
cycles.
The transmitting processor stars by sending the ID of the receiving processor with which it wants
to communicate as data with the multiprocessor bit set to 1. Next the transmitting processor sends
transmit data with the multiprocessor bit cleared to 0.
Receiving processors skip incoming data until they receive data with the multiprocessor bit set to
1. When they receive data with the multiprocessor bit set to 1, receiving processors compare the
data with their IDs. Processors with IDs not matching the received data skip further incoming data
until they again receive data with the multiprocessor bit set to 1. Multiple processors can send and
receive data in this way.
Figure 13.9 shows an example of communication among different processors using a
multiprocessor format.
Communication Formats: Four formats are available. Parity bit settings are ignored when a
multiprocessor format is selected. For details see table 13.10.
Clock: See the description of asynchronous mode.
Rev.5.00 Sep. 12, 2007 Page 466 of 764
REJ09B0396-0500