HD6413007F20 Datasheet, PDF (697/798 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

Appendix B Internal I/O Registers
DTCR0A⎯Data Transfer Control Register 0A (cont)
H'FFF27
• Full address mode
Bit
7
6
DTE
DTSZ
Initial value
0
0
Read/Write R/W
R/W
5
SAID
0
R/W
4
SAIDE
0
R/W
3
DTIE
0
R/W
2
DTS2A
0
R/W
1
DTS1A
0
R/W
0
DTS0A
0
R/W
DMAC0
Data transfer select 0A
0 Normal mode
1 Block transfer mode
Data transfer select 2A and 1A
Set both bits to 1
Data transfer interrupt enable
0 Interrupt requested by DTE bit is disabled
1 Interrupt requested by DTE bit is enabled
Source address increment/decrement (bit 5)
Source address increment/decrement enable (bit 4)
Bit 5 Bit 4
SAID SAIDE
Increment/Decrement Enable
0 MARA is held fixed
0
1 ^{Incremented: If DTSZ = 0, MARA is incremented by 1 after each transfer}
If DTSZ = 1, MARA is incremented by 2 after each transfer
0 MARA is held fixed
1
1 ^{Decremented: If DTSZ = 0, MARA is decremented by 1 after each transfer}
If DTSZ = 1, MARA is decremented by 2 after each transfer
Data transfer size
0 Byte-size transfer
1 Word-size transfer
Data transfer enable
0 Data transfer is disabled
1 Data transfer is enabled
Rev.5.00 Sep. 12, 2007 Page 667 of 764
REJ09B0396-0500