HD6413007F20 Datasheet, PDF (252/798 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

7. DMA Controller
If M (1 to 255) is the size of the block transferred at each request and N (1 to 65,536) is the
number of blocks to be transferred, then ETCRAH and ETCRAL should initially be set to M and
ETCRB should initially be set to N.
Figure 7.10 illustrates how block transfer mode operates. In this figure, bit TMS is cleared to 0,
meaning the block area is the destination.
T_A
Block 1
B_A
Transfer
Block area
Address T _B
Address B _B
Block 2
M bytes or words are
transferred per request
Block N
Legend:
L _A = initial setting of MARA
L _B = initial setting of MARB
M = initial setting of ETCRAH and ETCRAL
N = initial setting of ETCRB
T_A = L_A
B _A = L _A + SAIDE • (−1)^SAID • (2 ^DTSZ • M − 1)
T_B
B_B
=
=
L_B
L_B
+
DAIDE
•
(−1)^DAID
• (2 ^DTSZ
• M − 1)
Figure 7.10 Operation in Block Transfer Mode
Rev.5.00 Sep. 12, 2007 Page 222 of 764
REJ09B0396-0500