HD6413007F20 Datasheet, PDF (268/798 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

7. DMA Controller
7.4.14 DMAC States in Reset State, Standby Modes, and Sleep Mode
When the chip is reset or enters hardware standby mode or software standby mode, the DMAC is
initialized and halts. DMAC operations continue in sleep mode. Figure 7.24 shows the timing of a
cycle-steal transfer in sleep mode.
CPU cycle
DMAC cycle
Sleep mode
DMAC cycle
T₂ T_d T₁ T₂ T₁ T₂
T_d T₁ T₂ T₁ T₂
T_d
φ
Address bus
RD
HWR
Figure 7.24 Timing of Cycle-Steal Transfer in Sleep Mode
7.5 Interrupts
The DMAC generates only DMA-end interrupts. Table 7.13 lists the interrupts and their priority.
Table 7.13 DMAC Interrupts
Interrupt
DEND0A
DEND0B
DEND1A
DEND1B
Description
Short Address Mode
Full Address Mode
End of transfer on channel 0A End of transfer on channel 0
End of transfer on channel 0B ⎯
End of transfer on channel 1A End of transfer on channel 1
End of transfer on channel 1B ⎯
Interrupt
Priority
High
Low
Rev.5.00 Sep. 12, 2007 Page 238 of 764
REJ09B0396-0500