HD6413007F20 Datasheet, PDF (14/798 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

Item
14.3.4 Register
Settings
Smart Card Mode
Register (SCMR)
Settings:
Page
499
14.4 Usage Notes 511
Note on Block Transfer
Mode Support:
15.1 Overview
513
15.2.1 A/D Data
517
Registers A to D
(ADDRA to ADDRD)
16.1.3 Pin
536
Configuration
Table 16.1 D/A
Converter Pins
20.2.2 AC
581
Characteristics
Table 20.7 Control
Signal Timing
20.3.6 Timer
603
Input/Output Timing
A.3 Number of States 633
Required for Execution
Table A.4 Number of
Cycles per Instruction
Revision (See Manual for Details)
Description amended
With the direct convention type, the logic 1 level corresponds to
state Z and the logic 0 level to state A, and transfer is
performed in LSB-first order. In the example above, the first
character data is H'3B. The parity bit is 1, following the even
parity rule designated for smart cards.
Description added
The smart card interface installed in the H8/3006 and H8/3007
support an IC card (smart card) interface with provision for
ISO/IEC7816-3 T=0 (character transmission). Therefore, block
transfer operations are not supported (error signal transmission,
detection, and automatic data retransmission are not
performed).
Description amended
When the A/D converter is not used, it can be halted
independently to conserve power. For details see section 19.6,
Module Standby Function.
The H8/3006 and H8/3007 support 70/134-state conversion as
a high-speed conversion mode. Note that it differs in this
respect from the H8/3048 Group, which supports 134/266-state
conversion.
Description amended
The CPU can always read
the A/D data registers.
Table amended
Pin Name
Abbreviation I/O
Analog power
supply pin
AV_CC
Input
Function
Analog power supply and
reference voltage
Table amended
Item
NMI, IRQ pulse width
(in recovery from software standby mode)
Symbol
t_NMIW
Description amended
The timings of 16-bit and 8-bit timer are shown as follows:
Notes amended
Notes: 1. Not available in the H8/3006 and H8/3007.
2. n is the value set in register R4L or R4. The source
and destination are accessed n + 1 times each.
Rev.5.00 Sep. 12, 2007 Page xii of xxviii
REJ09B0396-0500