HD6413007F20 Datasheet, PDF (199/798 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

6. Bus Controller
Similar contention in a transition to self-refresh mode may prevent dependable strobe
waveform output. This can also be avoided by clearing the BRLW bit to 0 in BRCR.
• Immediately after self-refreshing is cleared, external bus release is possible during a given
period until the start of a CPU cycle. Attention must be paid to the RAS state to ensure that the
specification for the RAS precharge time immediately after self-refreshing is met.
External bus released
φ
Refresh cycle
CPU cycle
Refresh cycle
RFSH
Refresh
request
BACK
φ
BREQ
BACK
Address bus
Figure 6.33 Bus-Released State and Refresh Cycles
Software standby mode
Strobe
Figure 6.34 Bus-Released State and Software Standby Mode
Rev.5.00 Sep. 12, 2007 Page 169 of 764
REJ09B0396-0500