HD6413007F20 Datasheet, PDF (298/798 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

8. I/O Ports
Port A Data Register (PADR): PADR is an 8-bit readable/writable register that stores output
data for port A. When port A functions as an output port, the value of this register is output. When
a bit in PADDR is set to 1, if port A is read the value of the corresponding PADR bit is returned.
When a bit in PADDR is cleared to 0, if port A is read the corresponding pin level is read.
Bit
Initial value
Read/Write
7
PA ₇
0
R/W
6
PA ₆
0
R/W
5
PA ₅
0
R/W
4
PA ₄
0
R/W
3
PA ₃
0
R/W
2
PA ₂
0
R/W
1
PA ₁
0
R/W
0
PA ₀
0
R/W
Port A data 7 to 0
These bits store data for port A pins
PADR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it
retains its previous setting.
Table 8.12 Port A Pin Functions (Modes 1, 2)
Pin
PA /TP /
7
7
TIOCB
2
Pin Functions and Selection Method
Bit PWM2 in TMDR, bits IOB2 to IOB0 in TIOR2, bit NDER7 in NDERA, and bit
PA DDR select the pin function as follows.
7
16-bit timer
channel 2
(1) in table below
(2) in table below
settings
PA DDR
7
NDER7
⎯
0
1
1
⎯
⎯
0
1
Pin function
TIOCB output
2
PA
7
input
PA
7
output
TP
7
output
Note:
*
TIOCB input when IOB2 = 1 and PWM2 = 0.
2
16-bit timer
channel 2
(2)
(1)
settings
TIOCB₂ input*
(2)
IOB2
0
1
IOB1
0
0
1
⎯
IOB0
0
1
⎯
⎯
Rev.5.00 Sep. 12, 2007 Page 268 of 764
REJ09B0396-0500