HD6413007F20 Datasheet, PDF (530/798 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

14. Smart Card Interface
where, N: BRR setting (0 ≤ N ≤ 255)
B: Bit rate (bit/s)
φ: Operating frequency (MHz)
n: See table 14.4
Table 14.4 n-Values of CKS1 and CKS0 Settings
n
CKS1
CKS0
0
0
0
1
1
2
1
0
3
1
Note: If the gear function is used to divide the clock frequency, use the divided frequency to
calculate the bit rate. The equation above applies directly to 1/1 frequency division.
Table 14.5 Bit Rates (bits/s) for Various BRR Settings (When n = 0)
φ (MHz)
N
7.1424 10.00 10.7136 13.00 14.2848
0
9600.0 13440.9 14400.0 17473.1 19200.0
1
4800.0 6720.4 7200.0 8736.6 9600.0
2
3200.0 4480.3 4800.0 5824.4 6400.0
Note: Bit rates are rounded off to one decimal place.
16.00
21505.4
10752.7
7168.5
18.00
24193.5
12096.8
8064.5
20.00
26881.7
13440.9
8960.6
The following equation calculates the bit rate register (BRR) setting from the operating frequency
and bit rate. N is an integer from 0 to 255, specifying the value with the smaller error.
φ
N=
× 10⁶ – 1
1488 × 2^2n–1 × B
Table 14.6 BRR Settings for Typical Bit Rates (bits/s) (When n = 0)
7.1424
bit/s N Error
9600 0 0.00
10.00
N Error
1 30
10.7136
N Error
1 25
φ (MHz)
13.00 14.2848
N Error N Error
1 8.99 1 0.00
16.00
N Error
1 12.01
18.00
N Error
2 15.99
20.00
N Error
2 6.66
Rev.5.00 Sep. 12, 2007 Page 500 of 764
REJ09B0396-0500