HD6413007F20 Datasheet, PDF (18/798 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

2.8.6 Reset State ........................................................................................................... 54
2.8.7 Power-Down State ............................................................................................... 54
2.9 Basic Operational Timing ................................................................................................. 55
2.9.1 Overview.............................................................................................................. 55
2.9.2 On-Chip Memory Access Timing........................................................................ 55
2.9.3 On-Chip Supporting Module Access Timing ...................................................... 56
2.9.4 Access to External Address Space ....................................................................... 57
Section 3 MCU Operating Modes .................................................................................. 59
3.1 Overview........................................................................................................................... 59
3.1.1 Operating Mode Selection ................................................................................... 59
3.1.2 Register Configuration......................................................................................... 60
3.2 Mode Control Register (MDCR) ...................................................................................... 60
3.3 System Control Register (SYSCR) ................................................................................... 61
3.4 Operating Mode Descriptions ........................................................................................... 63
3.4.1 Mode 1 ................................................................................................................. 63
3.4.2 Mode 2 ................................................................................................................. 63
3.4.3 Mode 3 ................................................................................................................. 64
3.4.4 Mode 4 ................................................................................................................. 64
3.5 Pin Functions in Each Operating Mode ............................................................................ 64
3.6 Memory Map in Each Operating Mode ............................................................................ 65
3.6.1 Note on Reserved Areas....................................................................................... 65
Section 4 Exception Handling ......................................................................................... 69
4.1 Overview........................................................................................................................... 69
4.1.1 Exception Handling Types and Priority............................................................... 69
4.1.2 Exception Handling Operation............................................................................. 69
4.1.3 Exception Vector Table ....................................................................................... 70
4.2 Reset.................................................................................................................................. 72
4.2.1 Overview.............................................................................................................. 72
4.2.2 Reset Sequence .................................................................................................... 72
4.2.3 Interrupts after Reset............................................................................................ 74
4.3 Interrupts........................................................................................................................... 75
4.4 Trap Instruction................................................................................................................. 76
4.5 Stack Status after Exception Handling.............................................................................. 76
4.6 Notes on Stack Usage ....................................................................................................... 77
Section 5 Interrupt Controller .......................................................................................... 79
5.1 Overview........................................................................................................................... 79
5.1.1 Features................................................................................................................ 79
Rev.5.00 Sep. 12, 2007 Page xvi of xxviii
REJ09B0396-0500