HD6413007F20 Datasheet, PDF (364/798 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

9. 16-Bit Timer
9.5 Interrupts
The 16-bit timer has two types of interrupts: input capture/compare match interrupts, and overflow
interrupts.
9.5.1 Setting of Status Flags
Timing of Setting of IMFA and IMFB at Compare Match: IMFA and IMFB are set to 1 by a
compare match signal generated when 16TCNT matches a general register (GR). The compare
match signal is generated in the last state in which the values match (when 16TCNT is updated
from the matching count to the next count). Therefore, when 16TCNT matches a general register,
the compare match signal is not generated until the next 16TCNT clock input. Figure 9.33 shows
the timing of the setting of IMFA and IMFB.
φ
16TCNT input
clock
16TCNT
N
N+1
GR
N
Compare
match signal
IMF
IMI
Figure 9.33 Timing of Setting of IMFA and IMFB by Compare Match
Rev.5.00 Sep. 12, 2007 Page 334 of 764
REJ09B0396-0500