HD6413007F20 Datasheet, PDF (307/798 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

8. I/O Ports
Pin
PA /TP /
0
0
TCLKA/
TEND
0
Pin Functions and Selection Method
Bit MDF in TMDR, bits TPSC2 to TPSC0 in 16TCR2 to 16TCR0 of the 16-bit timer,
bits CKS2 to CKS0 in 8TCR1 of the 8-bit timer, bit NDER0 in NDERA, and bit
PA₀DDR select the pin function as follows.
PA₀DDR
0
1
NDER0
⎯
0
1
Pin function
PA₀ input
PA₀ output
TCLKA input*¹
TP₀ output
TEND
0
output*²
Notes: 1. TCLKA input when MDF = 1 in TMDR, or TPSC2 = 1, TPSC1 = 0 and
TPSC0 = 0 in any of 16TCR2 to 16TCR0, or bits CKS2 to CKS0 in
8TCR0 are as shown in (1) in the table below.
2. When an external request is specified as a DMAC activation source,
TEND output regardless of bits PA DDR and NDER0.
0
0
8-bit timer
channel 1
(2)
(1)
settings
CKS2
0
1
CKS1
⎯
0
1
CKS0
⎯
0
1
⎯
8.8 Port B
8.8.1 Overview
Port B is an 8-bit input/output port that is also used for output (TP₁₅ to TP₈) from the
programmable timing pattern controller (TPC), input/output (TMIO₃, TMO₂, TMIO₁, TMO₀) by
the
8-bit
timer,
CS
7
to
CS
4
output,
input
(DREQ₁,
DREQ₀)
to
the
DMA
controller
(DMAC),
input
and output (TxD₂, RxD₂, SCK₂) by serial communication interface channel 2 (SCI2), and output
(UCAS, LCAS) by the DRAM interface. See table 8.16 for the selection of pin functions.
A
reset
or
hardware
standby
transition
leaves
port
B
as
an
input
port.
For
output
of
CS
7
to
CS
4
in
modes 1 to 4, see section 6.3.4, Chip Select Signals. Pins not assigned to any of these functions are
available for generic input/output. When DRAM is connected to areas 2 to 5, the CS₄ and CS₅
output pins function as RAS output pins for each area. For details see section 6.5, DRAM
Interface. Figure 8.7 shows the pin configuration of port B.
Pins in port B can drive one TTL load and a 30-pF capacitive load. They can also drive darlington
transistor pair.
Rev.5.00 Sep. 12, 2007 Page 277 of 764
REJ09B0396-0500