HD6413007F20 Datasheet, PDF (713/798 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

Appendix B Internal I/O Registers
TISRC⎯Timer Interrupt Status Register C H'FFF66
16-Bit Timer (Common)
Bit
Initial value
Read/Write
7
6
5
4
3
2
1
0
⎯ OVIE2 OVIE1 OVIE0 ⎯ OVF2 OVF1 OVF0
1
0
0
0
1
0
0
0
⎯ R/W R/W R/W ⎯ R/(W)* R/(W)* R/(W)*
Overflow flag 0
0 ^{[Clearing condition]}
(Initial value)
Read OVF0 when OVF0 =1, then write 0 in OVF0
1 ^{[Setting condition]}
16TCNT0 overflowed from H'FFFF to H'0000
Overflow flag 1
0 ^{[Clearing condition]}
(Initial value)
Read OVF1 when OVF1 =1, then write 0 in OVF1
1 ^{[Setting condition]}
16TCNT1 overflowed from H'FFFF to H'0000
Overflow flag 2
0 ^{[Clearing condition]}
(Initial value)
Read OVF2 when OVF2 =1, then write 0 in OVF2
1 ^{[Setting condition]}
16TCNT2 overflowed from H'FFFF to H'0000 or
underflowed from H'0000 to H'FFFF
Overflow interrupt enable 0
0 OVI0 interrupt requested by OVF0 flag is disabled (Initial value)
1 OVI0 interrupt requested by OVF0 flag is enabled
Overflow interrupt enable 1
0 OVI1 interrupt requested by OVF1 flag is disabled (Initial value)
1 OVI1 interrupt requested by OVF1 flag is enabled
Overflow interrupt enable 2
0 OVI2 interrupt requested by OVF2 flag is disabled (Initial value)
1 OVI2 interrupt requested by OVF2 flag is enabled
Note: * Only 0 can be written, to clear the flag.
Rev.5.00 Sep. 12, 2007 Page 683 of 764
REJ09B0396-0500