HD6413007F20 Datasheet, PDF (158/798 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

6. Bus Controller
Bits 5 to 3⎯Refresh Counter Clock Select (CKS2 to CKS0): These bits select the clock to be
input to RTCNT from among 7 clocks obtained by dividing the system clock (φ). When the input
clock is selected with bits CKS2 to CKS0, RTCNT begins counting up.
Bit 5 Bit 4 Bit 3
CKS2 CKS1 CKS0 Description
0
0
0
Count operation halted
1
φ/2 used as counter clock
1
0
φ/8 used as counter clock
1
φ/32 used as counter clock
1
0
0
φ/128 used as counter clock
1
φ/512 used as counter clock
1
0
φ/2048 used as counter clock
1
φ/4096 used as counter clock
(Initial value)
Bits 2 to 0⎯Reserved: These bits cannot be modified and are always read as 1.
6.2.10 Refresh Timer Counter (RTCNT)
Bit
7
6
5
4
3
2
1
0
Initial value
Read/Write
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RTCNT is an 8-bit readable/writable up-counter.
RTCNT is incremented by an internal clock selected by bits CKS2 to CKS0 in RTMCSR. When
RTCNT matches RTCOR (compare match), the CMF flag in RTMCSR is set to 1 and RTCNT is
cleared to H'00. If the RCYCE bit in DRCRB is set to 1 at this time, a refresh cycle is started.
Also, if the CMIE bit in RTMCSR is set to 1, a compare match interrupt (CMI) is generated.
RTCNT is initialized to H'00 by a reset and in standby mode.
Rev.5.00 Sep. 12, 2007 Page 128 of 764
REJ09B0396-0500