HD6413007F20 Datasheet, PDF (629/798 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

20. Electrical Characteristics
20.3.4 DRAM Interface Bus Timing
DRAM interface bus timing is shown as follows:
• DRAM bus timing: read and write access
Figure 20.14 shows the timing of the read and write access.
• DRAM bus timing: CAS before RAS refresh
Figure 20.15 shows the timing of the CAS before RAS refresh.
• DRAM bus timing: self-refresh
Figure 20.16 shows the timing of the self-refresh.
Rev.5.00 Sep. 12, 2007 Page 599 of 764
REJ09B0396-0500