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| HD6413007F20 Datasheet, PDF (628/798 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series | |||
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20. Electrical Characteristics
T1
T2
Ï
tAD
A23 to A3,
CSn
A2 to A0
AS
RD
D15 to D0
tASD
tACC4
tAS1
tASD
tACC4
tAS1
tACC2
T3
T1
T2
tAD
tSD tAH
tASD
tAS1
tRDS
tACC2
T3
tSD
tAH
tRSD
tRDS
* tRDH
Note: * Specification from the earliest negation timing of A23 to A0, CSn, and RD.
Figure 20.12 Burst ROM Access Timing: Three-State Access
Ï
BREQ
BACK
tBRQS
tBRQS
tBACD1
tBACD2
A23 to A0,
AS, RD,
HWR, LWR
tBZD
tBZD
Figure 20.13 Bus-Release Mode Timing
Rev.5.00 Sep. 12, 2007 Page 598 of 764
REJ09B0396-0500
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