HD6413007F20 Datasheet, PDF (202/798 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

6. Bus Controller
Contention between RTCNT Write and Increment: If an increment pulse occurs in the T₃ state
of an RTCNT write cycle, writing takes priority and RTCNT is not incremented. See figure 6.38.
T1
T2
T3
φ
Address bus
RTCNT address
Internal write signal
RTCNT input clock
RTCNT
N
M
Counter write data
Figure 6.38 Contention between RTCNT Write and Increment
Contention between RTCOR Write and Compare Match: If a compare match occurs in the T₃
state of an RTCOR write cycle, writing takes priority and the compare match signal is inhibited.
See figure 6.39.
Rev.5.00 Sep. 12, 2007 Page 172 of 764
REJ09B0396-0500