HD6413007F20 Datasheet, PDF (747/798 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

Appendix B Internal I/O Registers
ADDRC H/L⎯A/D Data Register C H/L
H'FFFE4, H'FFFE5
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯
Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Read/Write R R R R R R R R R R R R R R R R
ADDRCH
ADDRCL
A/D
A/D conversion data
10-bit data giving an A/D conversion result
ADDRD H/L⎯A/D Data Register D H/L
H'FFFE6, H'FFFE7
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯
Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Read/Write R R R R R R R R R R R R R R R R
ADDRDH
ADDRDL
A/D
A/D conversion data
10-bit data giving an A/D conversion result
ADCR⎯A/D Control Register
H'FFFE9
A/D
Bit
7
6
5
4
3
2
1
0
TRGE
⎯
⎯
⎯
⎯
⎯
⎯
⎯
Initial value
0
1
1
1
1
1
1
0
Read/Write R/W
⎯
⎯
⎯
⎯
⎯
⎯
R/W
Trigger Enable
A/D conversion start by external trigger or 8-bit timer
0 _{compare match is disabled}
1
A/D conversion is started by falling edge of external
trigger signal (ADTRG) or 8-bit timer compare match
Rev.5.00 Sep. 12, 2007 Page 717 of 764
REJ09B0396-0500