HD6413007F20 Datasheet, PDF (41/798 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

1. Overview
Pin No.
Type
FP-100B
Symbol TFP-100B FP-100A I/O
Name and Function
DRAM
interface
DMA
controller
(DMAC)
16-bit
timer
RFSH
CS
2
to
CS
5
RD
87
89
89, 88, 5, 91, 90,
4
7, 6
70
72
HWR
71
UCAS 6
LWR
72
LCAS 7
DREQ , 5, 3
1
DREQ
0
TEND₁,
TEND
0
94, 93
TCLKD to 96 to 93
TCLKA
73
8
74
9
7, 5
96, 95
98 to95
Output Refresh: Indicates a refresh cycle
Output Row address strobe RAS: Row address
strobe signal for DRAM
Output Write enable WE: Write enable signal for
DRAM
Output Upper column address strobe UCAS:
Column address strobe signal for DRAM
Output Lower column address strobe LCAS:
Column address strobe signal for DRAM
Input DMA request 1 and 0: DMAC activation
requests
Output Transfer end 1 and 0: These signals indicate
that the DMAC has ended a data transfer.
Input Clock input D to A: External clock inputs
TIOCA to 99, 97, 95 1, 99, 97 Input/ Input capture/output compare A2 to A0:
2
TIOCA
0
output GRA2 to GRA0 output compare or input
capture, or PWM output
TIOCB₂ to 100, 98,
TIOCB 96
0
2, 100,
98
Input/ Input capture/output compare B2 to B0:
output GRB2 to GRB0 output compare or input
capture, or PWM output
8-bit timer TMO , 2, 4
0
TMO₂
TMIO₁, 3, 5
TMIO
3
4, 6
Output Compare match output: Compare match
output pins
5, 7
Input/ Input capture input/compare match output:
output Input capture input or compare match output
pins
TCLKD to 96 to 93 98 to 95 Input Counter external clock input: These pins
TCLKA
input an external clock to the counters.
Rev.5.00 Sep. 12, 2007 Page 11 of 764
REJ09B0396-0500