HD6413007F20 Datasheet, PDF (215/798 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

6. Bus Controller
6.11 Register and Pin Input Timing
6.11.1 Register Write Timing
ABWCR, ASTCR, WCRH, and WCRL Write Timing: Data written to ABWCR, ASTCR,
WCRH, and WCRL takes effect starting from the next bus cycle. Figure 6.47 shows the timing
when an instruction fetched from area 0 changes area 0 from three-state access to two-state access.
T1
T2
T3
T1
T2
T3
T1
T2
φ
Address bus
ASTCR address
3-state access to area 0
2-state access to area 0
Figure 6.47 ASTCR Write Timing
DDR and CSCR Write Timing: Data written to DDR or CSCR for the port corresponding to the
CSn pin to switch between CSn output and generic input takes effect starting from the T₃ state of
the
DDR
write
cycle.
Figure
6.48
shows
the
timing
when
the
CS
1
pin
is
changed
from
generic
input to CS₁ output.
T1
T2
T3
φ
Address bus
CS1
P8DDR address
High-impedance
Figure 6.48 DDR Write Timing
Rev.5.00 Sep. 12, 2007 Page 185 of 764
REJ09B0396-0500