HD6413007F20 Datasheet, PDF (245/798 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

Table 7.8 Register Functions in Repeat Mode
Register
23
MAR
Function
Activated by
SCI0 Receive-
Data-Full
Interrupt or
A/D Converter
Conversion
End Interrupt
Other
Activation
0 Destination
address
register
Source
address
register
23
All 1s
7
0 Source
IOAR ^address
register
Destination
address
register
7
0 Transfer counter
ETCRH
7
0
ETCRL
Initial transfer count
Legend:
MAR: Memory address register
IOAR: I/O address register
ETCR: Execute transfer count register
7. DMA Controller
Initial Setting Operation
Transfer
destination or
transfer source
start address
Incremented or
decremented at
each transfer
until ETCRH
reaches H'0000,
then restored to
initial value
Source or
destination
address
Held fixed
Number of
transfers
Decremented
once per
transfer until
H'0000 is
reached, then
reloaded from
ETCRL
Number of
transfers
Held fixed
In repeat mode ETCRH is used as the transfer counter while ETCRL holds the initial transfer
count. ETCRH is decremented by 1 at each transfer until it reaches H'00, then is reloaded from
ETCRL. MAR is also restored to its initial value, which is calculated from the DTSZ and DTID
bits in DTCR. Specifically, MAR is restored as follows:
MAR ← MAR − (−1)^DTID • 2^DTSZ • ETCRL
ETCRH and ETCRL should be initially set to the same value.
Rev.5.00 Sep. 12, 2007 Page 215 of 764
REJ09B0396-0500