HD6413007F20 Datasheet, PDF (714/798 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

Appendix B Internal I/O Registers
16TCR0⎯Timer Control Register 0
H'FFF68
16-Bit Timer Channel 0
Bit
Initial value
Read/Write
7
6
5
4
3
2
1
0
⎯ CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0
1
0
0
0
0
0
0
0
⎯ R/W R/W R/W R/W R/W R/W R/W
Timer prescaler 2 to 0
Bit 2
Bit 1
Bit 0
TPSC2 TPSC1 TPSC0
0
0
0
1
1
0
1
0
0
1
1
1
0
1
Description
Internal clock: Counts on φ
(Initial value)
Internal clock: Counts on φ/2
Internal clock: Counts on φ/4
Internal clock: Counts on φ/8
External clock A: Counts on TCLKA pin input
External clock B: Counts on TCLKB pin input
External clock C: Counts on TCLKC pin input
External clock D: Counts on TCLKD pin input
Clock edge 1 and 0
Bit 4
Bit 3
CKEG1 CKEG0
0
0
0
1
1
⎯
Description
Counts on rising edge
Counts on falling edge
Counts on both rising and falling edges
(Initial value)
Counter clear 1 and 0
Bit 6
Bit 5
CCLR1 CCLR0
Description
0
16TCNT clearing disabled
(Initial value)
0
1
16TCNT cleared by GRA compare match/input capture
0
16TCNT cleared by GRB compare match/input capture
1
Synchronous clear. 16TCNT cleared in synchronization with counter
1
clearing of other timers operating synchronously.
Rev.5.00 Sep. 12, 2007 Page 684 of 764
REJ09B0396-0500