HD6413007F20 Datasheet, PDF (240/798 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

7. DMA Controller
IOAR specifies the lower 8 bits of a fixed address. The upper 16 bits are all 1s. IOAR is not
incremented or decremented.
Figure 7.2 illustrates how I/O mode operates.
Address T
Transfer
IOAR
1 byte or word is
transferred per request
Address B
Legend:
L = initial setting of MAR
N = initial setting of ETCR
Address T = L
Address B = L + (−1) ^DTID • (2^DTSZ • N − 1)
Figure 7.2 Operation in I/O Mode
The transfer count is specified as a 16-bit value in ETCR. The ETCR value is decremented by 1 at
each transfer. When the ETCR value reaches H'0000, the DTE bit is cleared and the transfer ends.
If the DTIE bit is set to 1, a CPU interrupt is requested at this time. The maximum transfer count
is 65,536, obtained by setting ETCR to H'0000.
Rev.5.00 Sep. 12, 2007 Page 210 of 764
REJ09B0396-0500