HD6413007F20 Datasheet, PDF (382/798 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

10. 8-Bit Timers
Two of the compare match sources and two of the combined compare match/input capture sources
each have an independent interrupt vector. The remaining compare match interrupts, combined
compare match/input capture interrupts, and overflow interrupts have one interrupt vector for two
sources.
10.1.2 Block Diagram
The 8-bit timers are divided into two groups of two channels each: group 0 comprising channels 0
and 1, and group 1 comprising channels 2 and 3. Figure 10.1 shows a block diagram of 8-bit timer
group 0.
External clock
sources
TCLKA
TCLKC
Internal clock
sources
φ/8
φ/64
φ/8192
TMO₀
TMIO₁
Clock select
Clock 1
Clock 0
Compare match A1
TCORA0
TCORA1
Compare match A0 _{Comparator A0 Comparator A1}
Overflow 1
Overflow 0
8TCNT0
8TCNT1
Control logic
Compare match B1
Compare match B0 _{Comparator B0}
Input capture B1
Comparator B1
TCORB0
TCORB1
8TCSR0
8TCSR1
8TCR0
8TCR1
CMIA0
CMIB0
CMIA1/CMIB1
OVI0/OVI1
Interrupt signals
Legend:
TCORA:
TCORB:
8TCNT:
8TCSR:
8TCR:
Timer constant register A
Timer constant register B
Timer counter
Timer control/status register
Timer control register
Figure 10.1 Block Diagram of 8-Bit Timer Unit (Two Channels: Group 0)
Rev.5.00 Sep. 12, 2007 Page 352 of 764
REJ09B0396-0500