HD6413007F20 Datasheet, PDF (433/798 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

11. Programmable Timing Pattern Controller (TPC)
The output trigger period of a non-overlapping TPC output waveform is set in general register B
(GRB) in the 16-bit timer channel selected for output triggering. The non-overlap margin is set in
general register A (GRA). The output values change at compare match A and B. For details see
section 11.3.4, Non-Overlapping TPC Output.
TPMR is initialized to H'F0 by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bits 7 to 4⎯Reserved: These bits cannot be modified and are always read as 1.
Bit 3⎯Group 3 Non-Overlap (G3NOV): Selects normal or non-overlapping TPC output for
group 3 (TP₁₅ to TP₁₂).
Bit 3
G3NOV
0
1
Description
Normal TPC output in group 3 (output values change at
compare match A in the selected 16-bit timer channel)
Non-overlapping TPC output in group 3 (independent 1 and 0 output at
compare match A and B in the selected 16-bit timer channel)
(Initial value)
Bit 2⎯Group 2 Non-Overlap (G2NOV): Selects normal or non-overlapping TPC output for
group 2 (TP₁₁ to TP₈).
Bit 2
G2NOV
0
1
Description
Normal TPC output in group 2 (output values change at
compare match A in the selected 16-bit timer channel)
Non-overlapping TPC output in group 2 (independent 1 and 0 output at
compare match A and B in the selected 16-bit timer channel)
(Initial value)
Bit 1⎯Group 1 Non-Overlap (G1NOV): Selects normal or non-overlapping TPC output for
group 1 (TP₇ to TP₄).
Bit 1
G1NOV
0
1
Description
Normal TPC output in group 1 (output values change at
compare match A in the selected 16-bit timer channel)
Non-overlapping TPC output in group 1 (independent 1 and 0 output at
compare match A and B in the selected 16-bit timer channel)
(Initial value)
Rev.5.00 Sep. 12, 2007 Page 403 of 764
REJ09B0396-0500