HD6413007F20 Datasheet, PDF (211/798 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

6. Bus Controller
A setting whereby idle cycle insertion is not performed can be made only when RD and CSn do
not change simultaneously, or when it does not matter if they do.
φ
Address bus
Bus cycle A Bus cycle B
T₁ T₂ T₃ T₁ T₂
φ
Address bus
Bus cycle A Bus cycle B
T₁ T₂ T₃ T_i T₁ T₂
RD
RD
CSn
CSn
Simultaneous change of RD and CSn
Possibility of mutual overlap
(a) Idle cycle not inserted
(b) Idle cycle inserted
Figure 6.45 Example of Idle Cycle Operation (5)
6.9.2 Pin States in Idle Cycle
Table 6.11 shows the pin states in an idle cycle.
Table 6.11 Pin States in Idle Cycle
Pins
Pin State
A to A
23
0
D to D
15
0
CS
n
UCAS, LCAS
AS
RD
HWR
LWR
Next cycle address value
High impedance
High*
High
High
High
High
High
Note: * Remains low in DRAM space RAS down mode.
Rev.5.00 Sep. 12, 2007 Page 181 of 764
REJ09B0396-0500