HD6413007F20 Datasheet, PDF (188/798 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

6. Bus Controller
φ
DRAM access cycle
RASn
φ
(a) Access to DRAM space with a different row address
CBR refresh cycle
RASn
φ
(b) CAS-before-RAS refresh cycle
DRCRA write cycle
RASn
(c) BE bit or RDM bit cleared to 0 in DRCRA
External bus released
φ
RASn
High-impedance
(d) External bus released
Note: n = 2 to 5
Figure 6.22 RASn Negation Timing when RAS Down Mode Is Selected
Rev.5.00 Sep. 12, 2007 Page 158 of 764
REJ09B0396-0500