HD6413007F20 Datasheet, PDF (200/798 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

6. Bus Controller
Oscillation stabilization CPU internal cycle
time on exit from software (period in which external
standby mode
bus can be released)
CPU cycle
φ
Address bus
@SP
RAS
CAS
Figure 6.35 Self-Refresh Clearing
6.6 Interval Timer
6.6.1 Operation
When DRAM is not connected to the H8/3006 and H8/3007 chip, the refresh timer can be used as
an interval timer by clearing bits DRAS2 to DRAS0 in DRCRA to 0. After setting RTCOR,
selection a clock source with bits CKS2 to CKS0 in RTMCSR, and set the CMIE bit to 1.
Timing of Setting of Compare Match Flag and Clearing by Compare Match: The CMF flag
in RTMCSR is set to 1 by a compare match output when the RTCOR and RTCNT values match.
The compare match signal is generated in the last state in which the values match (when RTCNT
is updated from the matching value to a new value). Accordingly, when RTCNT and RTCOR
match, the compare match signal is not generated until the next counter clock pulse. Figure 6.36
shows the timing.
Rev.5.00 Sep. 12, 2007 Page 170 of 764
REJ09B0396-0500