HD6413007F20 Datasheet, PDF (390/798 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

10. 8-Bit Timers
When CKS2, CKS1, CKS0 = 1, 0, 0, channels 0 and 1 and channels 2 and 3 are cascaded.
The incrementing clock source is different when 8TCR0 and 8TCR2 are set, and when 8TCR1 and
8TCR3 are set.
Bit 2
CKS2
Bit 1
CKS1
Bit 0
CKS0
Description
0
0
0
Clock input disabled
(Initial value)
1
Internal clock, counted on falling edge of φ/8
1
0
Internal clock, counted on falling edge of φ/64
1
Internal clock, counted on falling edge of φ/8192
1
0
0
Channel 0 (16-bit count mode): Count on 8TCNT1 overflow
signal*¹
Channel 1 (compare match count mode): Count on 8TCNT0
compare match A*¹
Channel 2 (16-bit count mode): Count on 8TCNT3 overflow
signal*²
Channel 3 (compare match count mode): Count on 8TCNT2
compare match A*²
1
External clock, counted on rising edge
1
0
External clock, counted on falling edge
1
External clock, counted on both rising and falling edges
Notes: 1. If the clock input of channel 0 is the 8TCNT1 overflow signal and that of channel 1 is the
8TCNT0 compare match signal, no incrementing clock is generated. Do not use this
setting.
2. If the clock input of channel 2 is the 8TCNT3 overflow signal and that of channel 3 is the
8TCNT2 compare match signal, no incrementing clock is generated. Do not use this
setting.
Rev.5.00 Sep. 12, 2007 Page 360 of 764
REJ09B0396-0500