HD6413007F20 Datasheet, PDF (454/798 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

12. Watchdog Timer
12.5 Usage Notes
Contention between TCNT Write and Increment: If a timer counter clock pulse is generated
during the T₃ state of a write cycle to TCNT, the write takes priority and the timer count is not
incremented. See figure 12.8.
CPU: TCNT write cycle
T₁
T₂
T₃
φ
TCNT
Internal write
signal
TCNT input
clock
TCNT
N
M
Counter write data
Figure 12.8 Contention between TCNT Write and Count up
Changing CKS2 to CKS0 Bit: Halt TCNT by clearing the TME bit to 0 in TCSR before
changing the values of bits CKS2 to CKS0.
Rev.5.00 Sep. 12, 2007 Page 424 of 764
REJ09B0396-0500