HD6413007F20 Datasheet, PDF (192/798 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

6. Bus Controller
Use the RLW bit in DRCRB to adjust the RAS signal width. A single refresh wait state (T_RW) can
be inserted between the T_R1 state and T_R2 state by setting the RLW bit to 1.
The RLW bit setting is valid only for CBR refresh cycles, and does not affect DRAM read/write
cycles. The number of states in the CBR refresh cycle is not affected by the settings in ASTCR,
WCRH, or WCRL, or by the state of the WAIT pin.
Figure 6.27 shows the timing when the TPC bit and RLW bit are both set to 1.
TRp1
TRP2
TR1
TRW
TR2
φ
Address bus
CSn(RAS)
PB4/PB5
(UCAS/LCAS)
RD(WE)
RFSH
AS
Area 2 start address
High
High
Figure 6.27 CBR Refresh Timing (CSEL = 0, TPC = 1, RLW = 1)
DRAM must be refreshed immediately after powering on in order to stabilize its internal state.
When using the H8/3006 and H8/3007 CAS-before-RAS refresh function, therefore, a DRAM
stabilization period should be provided by means of interrupts by another timer module, or by
counting the number of times bit 7 (CMF) of RTMCSR is set, for instance, immediately after bits
DRAS2 to DRAS0 have been set in DRCRA.
Rev.5.00 Sep. 12, 2007 Page 162 of 764
REJ09B0396-0500