HD6413007F20 Datasheet, PDF (371/798 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

9. 16-Bit Timer
Contention between General Register Write and Compare Match: If a compare match occurs
in the T₃ state of a general register write cycle, writing takes priority and the compare match signal
is inhibited. See figure 9.40.
General register write cycle
T₁
T₂
T₃
φ
Address bus
GR address
Internal write signal
16TCNT
N
N+1
GR
Compare match signal
N
M
General register write data
Inhibited
Figure 9.40 Contention between General Register Write and Compare Match
Rev.5.00 Sep. 12, 2007 Page 341 of 764
REJ09B0396-0500