HD6413007F20 Datasheet, PDF (220/798 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

7. DMA Controller
7.1.4 Pin Configuration
Table 7.2 lists the DMAC pins.
Table 7.2 DMAC Pins
Channel Name
Abbrevia- Input/
tion
Output
Function
0
1
Note:
DMA request 0
DREQ
0
Input
External request for DMAC channel 0
Transfer end 0 TEND
0
Output Transfer end on DMAC channel 0
DMA request 1
DREQ
1
Input
External request for DMAC channel 1
Transfer end 1
TEND
1
Output Transfer end on DMAC channel 1
External requests cannot be made to channel A in short address mode.
7.1.5 Register Configuration
Table 7.3 lists the DMAC registers.
Table 7.3 DMAC Registers
Channel Address* Name
Abbreviation R/W Initial Value
0
H'FFF20 Memory address register 0AR
MAR0AR
R/W Undetermined
H'FFF21 Memory address register 0AE
MAR0AE
R/W Undetermined
H'FFF22 Memory address register 0AH
MAR0AH
R/W Undetermined
H'FFF23 Memory address register 0AL
MAR0AL
R/W Undetermined
H'FFF26 I/O address register 0A
IOAR0A
R/W Undetermined
H'FFF24 Execute transfer count register 0AH ETCR0AH R/W Undetermined
H'FFF25 Execute transfer count register 0AL ETCR0AL R/W Undetermined
H'FFF27 Data transfer control register 0A DTCR0A
R/W H'00
H'FFF28 Memory address register 0BR
MAR0BR
R/W Undetermined
H'FFF29 Memory address register 0BE
MAR0BE
R/W Undetermined
H'FFF2A Memory address register 0BH
MAR0BH
R/W Undetermined
H'FFF2B Memory address register 0BL
MAR0BL
R/W Undetermined
H'FFF2E I/O address register 0B
IOAR0B
R/W Undetermined
H'FFF2C Execute transfer count register 0BH ETCR0BH R/W Undetermined
H'FFF2D Execute transfer count register 0BL ETCR0BL R/W Undetermined
H'FFF2F Data transfer control register 0B DTCR0B
R/W H'00
Rev.5.00 Sep. 12, 2007 Page 190 of 764
REJ09B0396-0500