HD6413007F20 Datasheet, PDF (349/798 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

9. 16-Bit Timer
• Free-running and periodic counter operation
A reset leaves the counters (16TCNTs) in 16-bit timer channels 0 to 2 all set as free-running
counters. A free-running counter starts counting up when the corresponding bit in TSTR is set
to 1. When the count overflows from H'FFFF to H'0000, the OVF flag is set to 1 in TISRC.
After the overflow, the counter continues counting up from H'0000. Figure 9.13 illustrates
free-running counting.
16TCNT value
H'FFFF
H'0000
STR0 to
STR2 bit
OVF
Time
Figure 9.13 Free-Running Counter Operation
When a channel is set to have its counter cleared by compare match, in that channel 16TCNT
operates as a periodic counter. Select the output compare function of GRA or GRB, set bit CCLR1
or CCLR0 in 16TCR to have the counter cleared by compare match, and set the count period in
GRA or GRB. After these settings, the counter starts counting up as a periodic counter when the
corresponding bit is set to 1 in TSTR. When the count matches GRA or GRB, the IMFA or IMFB
flag is set to 1 in TISRA/TISRB and the counter is cleared to H'0000. If the corresponding IMIEA
or IMIEB bit is set to 1 in TISRA/TISRB, a CPU interrupt is requested at this time. After the
compare match, 16TCNT continues counting up from H'0000. Figure 9.14 illustrates periodic
counting.
Rev.5.00 Sep. 12, 2007 Page 319 of 764
REJ09B0396-0500