HD6413007F20 Datasheet, PDF (546/798 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

15. A/D Converter
15.1.4 Register Configuration
Table 15.2 summarizes the A/D converter's registers.
Table 15.2 A/D Converter Registers
Address*¹
Name
Abbreviation
H'FFFE0
A/D data register AH
ADDRAH
H'FFFE1
A/D data register AL
ADDRAL
H'FFFE2
A/D data register BH
ADDRBH
H'FFFE3
A/D data register BL
ADDRBL
H'FFFE4
A/D data register CH
ADDRCH
H'FFFE5
A/D data register CL
ADDRCL
H'FFFE6
A/D data register DH
ADDRDH
H'FFFE7
A/D data register DL
ADDRDL
H'FFFE8
A/D control/status register
ADCSR
H'FFFE9
A/D control register
ADCR
Notes: 1. Lower 20 bits of the address in advanced mode.
2. Only 0 can be written in bit 7, to clear the flag.
R/W Initial Value
R
H'00
R
H'00
R
H'00
R
H'00
R
H'00
R
H'00
R
H'00
R
H'00
R/(W)*² H'00
R/W H'7E
15.2 Register Descriptions
15.2.1 A/D Data Registers A to D (ADDRA to ADDRD)
Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADDRn
AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯
Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Read/Write
(n = A to D)
RRRRRRRRRRRR RRRR
A/D conversion data
10-bit data giving an
A/D conversion result
Reserved bits
The four A/D data registers (ADDRA to ADDRD) are 16-bit read-only registers that store the
results of A/D conversion.
An A/D conversion produces 10-bit data, which is transferred for storage into the A/D data
register corresponding to the selected channel. The upper 8 bits of the result are stored in the upper
byte of the A/D data register. The lower 2 bits are stored in the lower byte. Bits 5 to 0 of an A/D
Rev.5.00 Sep. 12, 2007 Page 516 of 764
REJ09B0396-0500