HD6413007F20 Datasheet, PDF (187/798 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

6. Bus Controller
DRAM access
External space
access
DRAM access
Tp
Tr
Tc1
Tc2
T1
T2
Tc1
Tc2
φ
A23 to A0
AS
CSn (RAS)
PB4/PB5
(UCAS/LCAS)
D15 to D0
Note: n = 2 to 5
Figure 6.21 Example of Operation Timing in RAS Down Mode (CSEL = 0)
When RAS down mode is selected, the conditions for an asserted RASn signal to return to the
high level are as shown below. The timing in these cases is shown in figure 6.22.
⎯ When DRAM space with a different row address is accessed
⎯ Immediately before a CAS-before-RAS refresh cycle
⎯ When the BE bit or RDM bit is cleared to 0 in DRCRA
⎯ Immediately before release of the external bus
Rev.5.00 Sep. 12, 2007 Page 157 of 764
REJ09B0396-0500