HD6413007F20 Datasheet, PDF (197/798 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

6. Bus Controller
• Figure 6.31 shows typical interconnections when using two 4-Mbit DRAMs, and the
corresponding address map. The DRAMs used in this example are of the 9-bit row address ×
9-bit column address type. In this example, upper address decoding allows multiple DRAMs to
be connected to a single area. The RFSH pin is used in this case, since both DRAMs must be
refreshed simultaneously. However, note that RAS down mode cannot be used in this
interconnection example.
H8/3006 and H8/3007
CS2 (RAS2)
PB4 (UCAS)
PB5 (LCAS)
RD (WE)
RFSH
A19
A9-A1
2-CAS 4-Mbit DRAM
9-bit row address × 9-bit column address
× 16-bit organization
RAS
UCAS
LCAS
WE
No.1
A8-A0
D15-D0
D15-D0 _OE
RAS
UCAS
LCAS
WE
No.2
A8-A0
D15-D0
OE
Area 2
(a) Interconnections (example)
PB4
(UCAS)
15
H'400000
PB5
(LCAS)
87
0
DRAM (No.1)
H'47FFFE
H'480000
DRAM (No.2)
H'4FFFFE
H'500000
CS2 (RAS2)
Not used
H'5FFFFE
16-Mbyte mode
(b) Address map
Figure 6.31 Interconnections and Address Map for 2-CAS 4-Mbit DRAMs with × 16-Bit
Organization
Rev.5.00 Sep. 12, 2007 Page 167 of 764
REJ09B0396-0500