HD6413007F20 Datasheet, PDF (288/798 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

8. I/O Ports
When
bits
in
P8DDR
bit
are
set
to
1,
P8₄
to
P8₁
become
CS
0
to
CS
3
output
pins.
When
bits
in
P8DDR are cleared to 0, the corresponding pins become input ports. Following a reset P8₄
functions
as
the
CS
0
output,
while
the
other
three
pins
are
input
ports.
When the refresh enable bit (RFSHE) in DRCRA is set to 1, P8 is used for RFSH output. When
0
RFSHE is cleared to 0, P8₀ becomes an input/output port according to the P8DDR setting. For
details see table 8.8.
P8DDR is a write-only register. Its value cannot be read. All bits return 1 when read.
P8DDR is initialized to H'F0 by a reset and in hardware standby mode. In software standby mode
P8DDR retains its previous setting. Therefore, when port 8 functions as an input/output port, if a
transition is made to software standby mode while a P8DDR bit is set to 1, the corresponding pin
maintains its output state.
Port 8 Data Register (P8DR): P8DR is an 8-bit readable/writable register that stores output data
for port 8. When a bit in P8DDR is set to 1, if port 8 is read the value of the corresponding P8DR
bit is returned. When a bit in P8DDR is cleared to 0, if port 8 is read the corresponding pin level is
read.
Bits 7 to 5 are reserved. They cannot be modified and always are read as 1.
Bit
7
6
5
4
3
2
1
0
⎯
⎯
⎯
P8 ₄
P8 ₃
P8 ₂
P8 ₁
P8 ₀
Initial value
1
1
1
0
0
0
0
0
Read/Write
⎯
⎯
⎯
R/W
R/W
R/W
R/W
R/W
Reserved bits
Port 8 data 4 to 0
These bits store data
for port 8 pins
P8DR is initialized to H'E0 by a reset and in hardware standby mode. In software standby mode it
retains its previous setting.
Rev.5.00 Sep. 12, 2007 Page 258 of 764
REJ09B0396-0500