HD6413007F20 Datasheet, PDF (365/798 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

9. 16-Bit Timer
Timing of Setting of IMFA and IMFB by Input Capture: IMFA and IMFB are set to 1 by an
input capture signal. The 16TCNT contents are simultaneously transferred to the corresponding
general register. Figure 9.34 shows the timing.
φ
Input capture
signal
IMF
16TCNT
N
GR
N
IMI
Figure 9.34 Timing of Setting of IMFA and IMFB by Input Capture
Timing of Setting of Overflow Flag (OVF): OVF is set to 1 when 16TCNT overflows from
H'FFFF to H'0000 or underflows from H'0000 to H'FFFF. Figure 9.35 shows the timing.
φ
16TCNT
Overflow
signal
OVF
OVI
Figure 9.35 Timing of Setting of OVF
Rev.5.00 Sep. 12, 2007 Page 335 of 764
REJ09B0396-0500