HD6413007F20 Datasheet, PDF (186/798 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

6. Bus Controller
Table 6.9 Correspondence between Settings of MXC1 and MXC0 Bits and ABWCR, and
Row Address Compared in Burst Access
Operating Mode
Modes 1 and 2
(1-Mbyte)
Modes 3 and 4
(16-Mbyte)
Note: n = 2 to 5
DRCRB
MXC1 MXC0
0
0
1
1
0
1
0
0
1
1
0
1
ABWCR
ABWn
0
1
0
1
0
1
⎯
0
1
0
1
0
1
⎯
Bus Width
16 bits
8 bits
16 bits
8 bits
16 bits
8 bits
⎯
16 bits
8 bits
16 bits
8 bits
16 bits
8 bits
⎯
Compared Row Address
A19 to A9
A19 to A8
A19 to A10
A19 to A9
A19 to A11
A19 to A10
Illegal setting
A23 to A9
A23 to A8
A23 to A10
A23 to A9
A23 to A11
A23 to A10
Illegal setting
RAS Down Mode and RAS Up Mode: With DRAM provided with fast page mode, as long as
accesses are to the same row address, burst operation can be continued without interruption even if
accesses are not consecutive by holding the RAS signal low.
• RAS Down Mode
To select RAS down mode, set the BE and RDM bits to 1 in DRCRA. If access to DRAM
space is interrupted and another space is accessed, the RAS signal is held low during the
access to the other space, and burst access is performed if the row address of the next DRAM
space access is the same as the row address of the previous DRAM space access. Figure 6.21
shows an example of the timing in RAS down mode.
Rev.5.00 Sep. 12, 2007 Page 156 of 764
REJ09B0396-0500