HD6413007F20 Datasheet, PDF (178/798 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

6. Bus Controller
6.5.3 Address Multiplexing
When DRAM space is accessed, the row address and column address are multiplexed. The address
multiplexing method is selected with bits MXC1 and MXC0 in DRCRB according to the number
of bits in the DRAM column address. Table 6.6 shows the correspondence between the settings of
MXC1 and MXC0 and the address multiplexing method.
Table 6.6 Settings of Bits MXC1 and MXC0 and Address Multiplexing Method
DRCRB
Column
Address
Address Pins
MXC1 MXC0 Bits
Row
0
0
8 bits
address
1
9 bits
1
0
10 bits
1
Illegal
setting
A₂₃ to A₁₃ A₁₂ A₁₁ A₁₀ A₉ A₈ A₇ A₆ A₅ A₄ A₃ A₂ A₁ A₀
A₂₃ to A₁₃ A₂₀* A₁₉ A₁₈ A₁₇ A₁₆ A₁₅ A₁₄ A₁₃ A₁₂ A₁₁ A₁₀ A₉ A₈
A₂₃ to A₁₃ A₁₂ A₂₀* A₁₉ A₁₈ A₁₇ A₁₆ A₁₅ A₁₄ A₁₃ A₁₂ A₁₁ A₁₀ A₉
A₂₃ to A₁₃ A₁₂ A₁₁ A₂₀* A₁₉ A₁₈ A₁₇ A₁₆ A₁₅ A₁₄ A₁₃ A₁₂ A₁₁ A₁₀
⎯
⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯
Column ⎯ ⎯ ⎯
address
A₂₃ to A₁₃ A₁₂ A₁₁ A₁₀ A₉ A₈ A₇ A₆ A₅ A₄ A₃ A₂ A₁ A₀
Note: * Row address bit A₂₀ is not multiplexed in 1-Mbyte mode.
6.5.4 Data Bus
If the bit in ABWCR corresponding to an area designated as DRAM space is set to 1, that area is
designated as 8-bit DRAM space; if the bit is cleared to 0, the area is designated as 16-bit DRAM
space. In 16-bit DRAM space, × 16-bit organization DRAM can be connected directly.
In 8-bit DRAM space the upper half of the data bus, D₁₅ to D₈, is enabled, while in 16-bit DRAM
space both the upper and lower halves of the data bus, D₁₅ to D₀, are enabled.
Access sizes and data alignment are the same as for the basic bus interface: see section 6.4.2, Data
Size and Data Alignment.
Rev.5.00 Sep. 12, 2007 Page 148 of 764
REJ09B0396-0500