HD6413007F20 Datasheet, PDF (19/798 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

5.1.2 Block Diagram ..................................................................................................... 80
5.1.3 Pin Configuration................................................................................................. 81
5.1.4 Register Configuration......................................................................................... 81
5.2 Register Descriptions ........................................................................................................ 82
5.2.1 System Control Register (SYSCR) ...................................................................... 82
5.2.2 Interrupt Priority Registers A and B (IPRA, IPRB) ............................................. 83
5.2.3 IRQ Status Register (ISR).................................................................................... 89
5.2.4 IRQ Enable Register (IER) .................................................................................. 90
5.2.5 IRQ Sense Control Register (ISCR) .................................................................... 91
5.3 Interrupt Sources ............................................................................................................... 92
5.3.1 External Interrupts ............................................................................................... 92
5.3.2 Internal Interrupts................................................................................................. 93
5.3.3 Interrupt Vector Table.......................................................................................... 93
5.4 Interrupt Operation............................................................................................................ 97
5.4.1 Interrupt Handling Process................................................................................... 97
5.4.2 Interrupt Sequence ............................................................................................... 102
5.4.3 Interrupt Response Time...................................................................................... 103
5.5 Usage Notes ...................................................................................................................... 104
5.5.1 Contention between Interrupt and Interrupt-Disabling Instruction ...................... 104
5.5.2 Instructions that Inhibit Interrupts........................................................................ 105
5.5.3 Interrupts during EEPMOV Instruction Execution .............................................. 105
Section 6 Bus Controller.................................................................................................... 107
6.1 Overview........................................................................................................................... 107
6.1.1 Features................................................................................................................ 107
6.1.2 Block Diagram ..................................................................................................... 108
6.1.3 Pin Configuration................................................................................................. 110
6.1.4 Register Configuration......................................................................................... 111
6.2 Register Descriptions ........................................................................................................ 112
6.2.1 Bus Width Control Register (ABWCR)............................................................... 112
6.2.2 Access State Control Register (ASTCR) ............................................................. 113
6.2.3 Wait Control Registers H and L (WCRH, WCRL).............................................. 113
6.2.4 Bus Release Control Register (BRCR) ................................................................ 117
6.2.5 Bus Control Register (BCR) ................................................................................ 119
6.2.6 Chip Select Control Register (CSCR).................................................................. 121
6.2.7 DRAM Control Register A (DRCRA) ................................................................. 122
6.2.8 DRAM Control Register B (DRCRB) ................................................................. 124
6.2.9 Refresh Timer Control/Status Register (RTMCSR) ............................................ 127
6.2.10 Refresh Timer Counter (RTCNT)........................................................................ 128
6.2.11 Refresh Time Constant Register (RTCOR) ......................................................... 129
Rev.5.00 Sep. 12, 2007 Page xvii of xxviii
REJ09B0396-0500