HD6413007F20 Datasheet, PDF (109/798 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

5. Interrupt Controller
Section 5 Interrupt Controller
5.1 Overview
5.1.1 Features
The interrupt controller has the following features:
• Interrupt priority registers (IPRs) for setting interrupt priorities
Interrupts other than NMI can be assigned to two priority levels on a module-by-module basis
in interrupt priority registers A and B (IPRA and IPRB).
• Three-level enable/disable state setting possible by means of the I and UI bits in the CPU's
condition code register (CCR) and the UE bit in the system control register (SYSCR)
• Seven external interrupt pins
NMI has the highest priority and is always accepted; either the rising or falling edge can be
selected. For each of IRQ₀ to IRQ₅, sensing of the falling edge or level sensing can be selected
independently.
Rev.5.00 Sep. 12, 2007 Page 79 of 764
REJ09B0396-0500