HD6413007F20 Datasheet, PDF (270/798 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

7. DMA Controller
7.6.3 Longword Access to Memory Address Registers
A memory address register can be accessed as longword data at the MARR address.
Example
MOV.L #LBL, ER0
MOV.L ER0, @MARR
Four byte accesses are performed. Note that the CPU may release the bus between the second byte
(MARE) and third byte (MARH).
Memory address registers should be written and read only when the DMAC is halted.
7.6.4 Note on Full Address Mode Setup
Full address mode is controlled by two registers: DTCRA and DTCRB. Care must be taken to
prevent the B channel from operating in short address mode during the register setup. The enable
bits (DTE and DTME) should not be set to 1 until the end of the setup procedure.
Rev.5.00 Sep. 12, 2007 Page 240 of 764
REJ09B0396-0500