HD6413007F20 Datasheet, PDF (239/798 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

7. DMA Controller
7.4.2 I/O Mode
I/O mode can be selected independently for each channel.
One byte or word is transferred at each transfer request in I/O mode. A designated number of these
transfers are executed. One address is specified in the memory address register (MAR), the other
in the I/O address register (IOAR). The direction of transfer is determined automatically from the
activation source. The transfer is from the address specified in IOAR to the address specified in
MAR if activated by an SCI channel 0 receive-data-full interrupt or an A/D converter conversion
end interrupt, and from the address specified in MAR to the address specified in IOAR otherwise.
Table 7.6 indicates the register functions in I/O mode.
Table 7.6 Register Functions in I/O Mode
Register
23
MAR
Function
Activated by
SCI0 Receive-
Data-Full
Interrupt or
A/D Converter
Conversion
End Interrupt
Other
Activation
0 Destination
address
register
Source
address
register
23
All 1s
7
0 Source
IOAR ^address
register
Destination
address
register
15
0 Transfer counter
ETCR
Legend:
MAR: Memory address register
IOAR: I/O address register
ETCR: Execute transfer count register
Initial Setting Operation
Destination or Incremented or
source address decremented
once per
transfer
Source or
destination
address
Held fixed
Number of
transfers
Decremented
once per
transfer until
H'0000 is
reached and
transfer ends
MAR and IOAR specify the source and destination addresses. MAR specifies a 24-bit source or
destination address, which is incremented or decremented as each byte or word is transferred.
Rev.5.00 Sep. 12, 2007 Page 209 of 764
REJ09B0396-0500