HD6413007F20 Datasheet, PDF (414/798 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

10. 8-Bit Timers
10.7.7 Contention between 8TCNT Byte Write and Increment in 16-Bit Count Mode
(Cascaded Connection)
If an increment pulse occurs in the T₂ or T₃ state of a 8TCNT byte write cycle in 16-bit count
mode, writing takes priority and 8TCNT is not incremented. The byte data for which a write was
not performed retains its previous value. Figure 10.24 shows the timing when an increment pulse
occurs in the T₂ state of a byte write to 8TCNTH.
8TCNTH byte write cycle
T1
T2
T3
φ
Address bus
8TCNTH address
Internal write signal
8TCNT input clock
8TCNTH
N
8TCNT write data
8TCNTL
X
X+1
Figure 10.24 Contention between 8TCNT Byte Write and Increment in 16-Bit Count Mode
Rev.5.00 Sep. 12, 2007 Page 384 of 764
REJ09B0396-0500