HD6413007F20 Datasheet, PDF (427/798 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

11. Programmable Timing Pattern Controller (TPC)
Same Trigger for TPC Output Groups 2 and 3: If TPC output groups 2 and 3 are triggered by
the same compare match event, the NDRB address is H'FFFA4. The upper 4 bits belong to group
3 and the lower 4 bits to group 2. Address H'FFFA6 consists entirely of reserved bits that cannot
be modified and always read 1.
Address H'FFFA4
Bit
Initial value
Read/Write
7
NDR15
0
R/W
6
NDR14
0
R/W
5
NDR13
0
R/W
4
NDR12
0
R/W
3
NDR11
0
R/W
2
NDR10
0
R/W
1
NDR9
0
R/W
0
NDR8
0
R/W
Address H'FFFA6
Next data 15 to 12
These bits store the next output
data for TPC output group 3
Bit
7
6
5
4
⎯
⎯
⎯
⎯
Initial value
1
1
1
1
Read/Write
⎯
⎯
⎯
⎯
Next data 11 to 8
These bits store the next output
data for TPC output group 2
3
2
1
0
⎯
⎯
⎯
⎯
1
1
1
1
⎯
⎯
⎯
⎯
Reserved bits
Different Triggers for TPC Output Groups 2 and 3: If TPC output groups 2 and 3 are triggered
by different compare match events, the address of the upper 4 bits of NDRB (group 3) is H'FFFA4
and the address of the lower 4 bits (group 2) is H'FFFA6. Bits 3 to 0 of address H'FFFA4 and bits
7 to 4 of address H'FFFA6 are reserved bits that cannot be modified and always read 1.
Address H'FFFA4
Bit
7
6
5
4
3
2
1
0
NDR15 NDR14 NDR13 NDR12 ⎯
⎯
⎯
⎯
Initial value
0
0
0
0
1
1
1
1
Read/Write
R/W
R/W R/W
R/W
⎯
⎯
⎯
⎯
Next data 15 to 12
These bits store the next output
data for TPC output group 3
Reserved bits
Rev.5.00 Sep. 12, 2007 Page 397 of 764
REJ09B0396-0500