HD6413007F20 Datasheet, PDF (20/798 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

6.3 Operation .......................................................................................................................... 130
6.3.1 Area Division....................................................................................................... 130
6.3.2 Bus Specifications................................................................................................ 132
6.3.3 Memory Interfaces............................................................................................... 133
6.3.4 Chip Select Signals .............................................................................................. 133
6.4 Basic Bus Interface ........................................................................................................... 134
6.4.1 Overview.............................................................................................................. 134
6.4.2 Data Size and Data Alignment............................................................................. 134
6.4.3 Valid Strobes........................................................................................................ 136
6.4.4 Memory Areas ..................................................................................................... 136
6.4.5 Basic Bus Control Signal Timing ........................................................................ 138
6.4.6 Wait Control ........................................................................................................ 145
6.5 DRAM Interface ............................................................................................................... 147
6.5.1 Overview.............................................................................................................. 147
6.5.2 DRAM Space and RAS Output Pin Settings ....................................................... 147
6.5.3 Address Multiplexing........................................................................................... 148
6.5.4 Data Bus............................................................................................................... 148
6.5.5 Pins Used for DRAM Interface............................................................................ 149
6.5.6 Basic Timing........................................................................................................ 149
6.5.7 Precharge State Control ....................................................................................... 151
6.5.8 Wait Control ........................................................................................................ 152
6.5.9 Byte Access Control and CAS Output Pin........................................................... 153
6.5.10 Burst Operation.................................................................................................... 154
6.5.11 Refresh Control.................................................................................................... 160
6.5.12 Examples of Use .................................................................................................. 164
6.5.13 Usage Notes ......................................................................................................... 168
6.6 Interval Timer ................................................................................................................... 170
6.6.1 Operation ............................................................................................................. 170
6.7 Interrupt Sources............................................................................................................... 175
6.8 Burst ROM Interface......................................................................................................... 176
6.8.1 Overview.............................................................................................................. 176
6.8.2 Basic Timing........................................................................................................ 176
6.8.3 Wait Control ........................................................................................................ 177
6.9 Idle Cycle.......................................................................................................................... 178
6.9.1 Operation ............................................................................................................. 178
6.9.2 Pin States in Idle Cycle ........................................................................................ 181
6.10 Bus Arbiter........................................................................................................................ 182
6.10.1 Operation ............................................................................................................. 182
6.11 Register and Pin Input Timing .......................................................................................... 185
6.11.1 Register Write Timing ......................................................................................... 185
Rev.5.00 Sep. 12, 2007 Page xviii of xxviii
REJ09B0396-0500