HD6413007F20 Datasheet, PDF (451/798 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

12. Watchdog Timer
A watchdog reset has the same vector as a reset generated by input at the RES pin. Software can
distinguish a RES reset from a watchdog reset by checking the WRST bit in RSTCSR.
If a RES reset and a watchdog reset occur simultaneously, the RES reset takes priority.
H'FF
WDT overflow
TCNT count
value
TME set to 1
H'00
Internal
reset signal
Start
OVF = 1
H'00 written
in TCNT
Reset
H'00 written
in TCNT
RESO
518 states
132 states
Figure 12.4 Operation in Watchdog Timer Mode
Rev.5.00 Sep. 12, 2007 Page 421 of 764
REJ09B0396-0500