HD6413007F20 Datasheet, PDF (730/798 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

Appendix B Internal I/O Registers
TPMR⎯TPC Output Mode Register
Bit
7
6
5
⎯
⎯
⎯
Initial value
1
1
1
Read/Write
⎯
⎯
⎯
H'FFFA0
4
3
⎯
G3NOV
1
0
⎯
R/W
2
G2NOV
0
R/W
TPC
1
G1NOV
0
R/W
0
G0NOV
0
R/W
Group 0 non-overlap
Normal TPC output in group 0. Output values
0 ^{change at compare match A in the selected}
16-bit timer channel
Non-overlapping TPC output in group 0,
1 ^{controlled by compare match A and B in the}
selected 16-bit timer channel
Group 1 non-overlap
0
Normal TPC output in group 1. Output values change
at compare match A in the selected 16-bit timer channel
1
Non-overlapping TPC output in group 1, controlled by
compare match A and B in the selected 16-bit timer channel
Group 2 non-overlap
0
Normal TPC output in group 2. Output values change at
compare match A in the selected 16-bit timer channel
1
Non-overlapping TPC output in group 2, controlled by
compare match A and B in the selected 16-bit timer channel
Group 3 non-overlap
0
Normal TPC output in group 3. Output values change at
compare match A in the selected 16-bit timer channel
1
Non-overlapping TPC output in group 3, controlled by
compare match A and B in the selected 16-bit timer channel
Rev.5.00 Sep. 12, 2007 Page 700 of 764
REJ09B0396-0500