HD6413007F20 Datasheet, PDF (166/798 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

6. Bus Controller
6.4.3 Valid Strobes
Table 6.4 shows the data buses used, and the valid strobes, for the access spaces.
In a read, the RD signal is valid for both the upper and the lower half of the data bus.
In a write, the HWR signal is valid for the upper half of the data bus, and the LWR signal for the
lower half.
Table 6.4 Data Buses Used and Valid Strobes
Area
8-bit
access
area
Access
Size Read/Write
Byte Read
Write
Address
⎯
⎯
Valid Strobe
RD
HWR
Upper Data Bus Lower Data Bus
(D to D )
15
8
(D to D )
7
0
Valid
Invalid
Undetermined
data
16-bit
access
area
Byte Read
Write
Even
Odd
Even
RD
HWR
Valid
Invalid
Valid
Invalid
Valid
Undetermined
data
Odd
LWR
Undetermined Valid
data
Word Read
⎯
RD
Valid
Valid
Write
⎯
HWR, LWR Valid
Valid
Notes: 1. Undetermined data means that unpredictable data is output.
2. Invalid means that the bus is in the input state and the input is ignored.
6.4.4 Memory Areas
The initial state of each area is basic bus interface, three-state access space. The initial bus width is
selected according to the operating mode. The bus specifications described here cover basic items
only, and the following sections should be referred to for further details: 6.4, Basic Bus Interface,
6.5, DRAM Interface, 6.8, Burst ROM Interface.
Area
0:
When
area
0
external
space
is
accessed,
the
CS
0
signal
can
be
output.
Either basic bus interface or burst ROM interface can be selected for area 0.
The size of area 0 is 128 kbytes in modes 1 and 2, and 2 Mbytes in modes 3 and 4.
Areas 1 and 6: When area 1 and 6 external space is accessed, the CS₁ and CS₆ pin signals
respectively can be output.
Only the basic bus interface can be used for areas 1 and 6.
Rev.5.00 Sep. 12, 2007 Page 136 of 764
REJ09B0396-0500